The present invention relates to a semiconductor device and, more particularly, to a technology which is effective when applied to a semiconductor device including a nonvolatile memory.
An electrically rewritable nonvolatile memory, such as EEPROM (Electrically Erasable Programmable Read Only Memory) or a flash memory, allows on-board rewriting of a program to allow a reduction in development period and an improvement in development efficiency. Besides, the electrically rewritable nonvolatile memory also has a wider range of applications for various uses, such as production of small quantities of many items, destination specific tuning, and post-shipment program update. There is also a growing need for a semiconductor device in which a main circuit and a nonvolatile memory for storing desired data of a relatively small capacity related to the main circuit are embedded in the same semiconductor chip.
An example of a nonvolatile memory cell is a memory cell comprising two transistors, which are a memory transistor for retaining data, and a select transistor for selecting the memory transistor as a so-called memory bit. Of the two transistors, the memory transistor typically has a gate made of polysilicon and having a double-layer structure, in which a floating gate for holding electrons are provided in the lower layer, while a control gate for controlling the potential of the floating gate is provided in the upper layer. Under the floating gate, a tunnel portion comprising an extremely thin insulating film is provided. The rewriting (writing and erasing) of data to such a memory cell is performed by allowing a FN (Fowlor Nordheim) tunnel current to flow via the tunnel portion and causing the injection of electrons into the floating gate or the emission of electrons from the floating gate.
Another example of the nonvolatile memory cell is a memory cell made of a single layer of polysilicon, which is described in, e.g., Japanese Unexamined Patent Publication No. 2007-110073 (Patent Document 1). In the nonvolatile memory cell described in Patent Document 1, a single-layer floating gate electrode is formed on the principal surface of a semiconductor substrate with an insulating film interposed therebetween. At respective positions in a plane of the floating gate electrode, a capacitor portion (capacitor element), a write/erase capacitor portion (write/erase element), and a read portion (read element) are arranged. Patent Document 1 discloses a structure in which rewriting of data is performed with the FN tunnel current of the entire surface of a channel in the data write/erase capacitor portion of the nonvolatile memory cell.
[Patent Document 1]
    Japanese Unexamined Patent Publication No. 2007-110073